74HC125D

Quad buffer/line driver; 3-state

The 74HC125; 74HCT125 is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A HIGH on nOE causes the outputs to assume a high impedance OFF-state. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V_CC.

Features and benefits

Wide supply voltage range from 2.0 to 6.0 V
CMOS low power dissipation
High noise immunity
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Complies with JEDEC standards:
- JESD8C (2.7 V to 3.6 V)
- JESD7A (2.0 V to 6.0 V)
Input levels:
- The 74HC125: CMOS levels
- The 74HCT125: TTL levels
ESD protection:
- HBM JESD22-A114F exceeds 2000 V
- MM JESD22-A115-A exceeds 200 V
Specified from -40 °C to +85 °C and from -40 °C to +125 °C

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SKU: 74HC125NXP SOIC Category: Analog & Logic ICs

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74HC04D

Hex inverter

The 74HC04; 74HCT04 is a hex inverter. The inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of V_CC.

Features and benefits

Wide supply voltage range from 2.0 V to 6.0 V
CMOS low power dissipation
High noise immunity
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Complies with JEDEC standards:
- JESD8C (2.7 V to 3.6 V)
- JESD7A (2.0 V to 6.0 V)
Input levels:
- For 74HC04: CMOS level
- For 74HCT04: TTL level
ESD protection:
- HBM JESD22-A114F exceeds 2000 V
- MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from -40 °C to +85 °C and from -40 °C to +125 °C

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74HC244D

Octal buffer/line driver; 3-state

The 74HC244; 74HCT244 is an 8-bit buffer/line driver with 3-state outputs. The device can be used as two 4-bit buffers or one 8-bit buffer. The device features two output enables (1OE and 2OE), each controlling four of the 3-state outputs. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of V_CC.

Features and benefits

Wide supply voltage range from 2.0 to 6.0 V
CMOS low power dissipation
High noise immunity
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Input levels:
- For 74HC244: CMOS level
- For 74HCT244: TTL level
Octal bus interface
Non-inverting 3-state outputs
Complies with JEDEC standards:
- JESD8C (2.7 V to 3.6 V)
- JESD7A (2.0 V to 6.0 V)
ESD protection:
- HBM JESD22-A114F exceeds 2000 V
- MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C

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74HC00D

Quad 2-input NAND gate

The 74HC00; 74HCT00 is a quad 2-input NAND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V_CC.

Features and benefits

Total power dissipation: ≤ 590 mW
Wide working voltage range: nominal 2.4 V to 75 V (E24 range)
Small plastic package s
Wide supply voltage range from 2.0 to 6.0 V
CMOS low power dissipation
High noise immunity
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Input levels:
- For 74HC00: CMOS level
- For 74HCT00: TTL level
Complies with JEDEC standards:
- JESD8C (2.7 V to 3.6 V)
- JESD7A (2.0 V to 6.0 V)
ESD protection:
- HBM JESD22-A114F exceeds 2000 V
- MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
uitable for surface-mounted design
Low differential resistance
AEC-Q101 qualified

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74HC164D

8-bit serial-in, parallel-out shift register

The 74HC164; 74HCT164 is an 8-bit serial-in/parallel-out shift register. The device features two serial data inputs (DSA and DSB), eight parallel data outputs (Q0 to Q7). Data is entered serially through DSA or DSB and either input can be used as an active HIGH enable for data entry through the other input. Data is shifted on the LOW-to-HIGH transitions of the clock (CP) input. A LOW on the master reset input (MR) clears the register and forces all outputs LOW, independently of other inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V_CC.

Features and benefits

Wide supply voltage range from 2.0 to 6.0 V
CMOS low power dissipation
High noise immunity
Input levels:
- For 74HC164: CMOS level
- For 74HCT164: TTL level
Gated serial data inputs
Asynchronous master reset
Complies with JEDEC standards
- JESD8C (2.7 V to 3.6 V)
- JESD7A (2.0 V to 6.0 V)
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
ESD protection:
- HBM JESD22-A114F exceeds 2000 V
- MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C.

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74HC08D

Quad 2-input AND gate

The 74HC08; 74HCT08 is a quad 2-input AND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V_CC.

Features and benefits

Wide supply voltage range from 2.0 V to 6.0 V
CMOS low power dissipation
High noise immunity
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Input levels:
- For 74HC08: CMOS level
- For 74HCT08: TTL level
Complies with JEDEC standards:
- JESD8C (2.7 V to 3.6 V)
- JESD7A (2.0 V to 6.0 V)
ESD protection:
- HBM JESD22-A114F exceeds 2000 V
- MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from -40 °C to +85 °C and from -40 °C to +125 °C

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74HC14D

Hex inverting Schmitt trigger

The 74HC14; 74HCT14 is a hex inverter with Schmitt-trigger inputs. This device features reduced input threshold levels to allow interfacing to TTL logic levels. Inputs also include clamp diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of V_CC. Schmitt trigger inputs transform slowly changing input signals into sharply defined jitter-free output signals.

Features and benefits

Wide supply voltage range from 2.0 to 6.0 V
CMOS low power dissipation
High noise immunity
Unlimited input rise and fall times
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Complies with JEDEC standards:
- JESD8C (2.7 V to 3.6 V)
- JESD7A (2.0 V to 6.0 V)
ESD protection:
- HBM JESD22-A114F exceeds 2000 V
- MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from -40 °C to +85 °C and from -40 °C to +125 °C

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74HC132D

Quad 2-input NAND Schmitt trigger

The 74HC132; 74HCT132 is a quad 2-input NAND gate with Schmitt-trigger inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V_CC. Schmitt trigger inputs transform slowly changing input signals into sharply defined jitter-free output signals.

Features and benefits

Wide supply voltage range from 2.0 to 6.0 V
CMOS low power dissipation
High noise immunity
Unlimited input rise and fall times
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Complies with JEDEC standards:
- JESD8C (2.7 V to 3.6 V)
- JESD7A (2.0 V to 6.0 V)
ESD protection:
- HBM JESD22-A114F exceeds 2000 V
- MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from −40 °C to +85 °C and from −40 °C to +125 °C

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74HC126D

Quad buffer/line driver; 3-state

The 74HC126; 74HCT126 is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A LOW on nOE causes the outputs to assume a high-impedance OFF-state. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V_CC.

Features and benefits

Wide supply voltage range from 2.0 to 6.0 V
CMOS low power dissipation
High noise immunity
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Inverting outputs
Complies with JEDEC standards:
- JESD8C (2.7 V to 3.6 V)
- JESD7A (2.0 V to 6.0 V)
Input levels:
- For 74HC126: CMOS levels
- For 74HCT126: TTL levels
ESD protection:
- HBM JESD22-A114F exceeds 2000 V
- MM JESD22-A115-A exceeds 200 V
Specified from -40 °C to +85 °C and from -40 °C to +125 °C

DOWNLOADS:

Datasheet

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