74HC244D - Image 1
Click to enlarge
74HC238D
74HC238D
Back to products
74HC245D
74HC245D

74HC244D

Octal buffer/line driver; 3-state

The 74HC244; 74HCT244 is an 8-bit buffer/line driver with 3-state outputs. The device can be used as two 4-bit buffers or one 8-bit buffer. The device features two output enables (1OE and 2OE), each controlling four of the 3-state outputs. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.

Features and benefits

  • Wide supply voltage range from 2.0 to 6.0 V
  • CMOS low power dissipation
  • High noise immunity
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
  • Input levels:
    • For 74HC244: CMOS level
    • For 74HCT244: TTL level
  • Octal bus interface
  • Non-inverting 3-state outputs
  • Complies with JEDEC standards:
    • JESD8C (2.7 V to 3.6 V)
    • JESD7A (2.0 V to 6.0 V)
  • ESD protection:
    • HBM JESD22-A114F exceeds 2000 V
    • MM JESD22-A115-A exceeds 200 V
  • Multiple package options
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

DOWNLOADS:

SKU: 74HC244NXP SOIC Category:
Shipping & Delivery

Related products

74HC00D

Quad 2-input NAND gate

The 74HC00; 74HCT00 is a quad 2-input NAND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

Features and benefits

  • Total power dissipation: ≤ 590 mW
  • Wide working voltage range: nominal 2.4 V to 75 V (E24 range)
  • Small plastic package s
  • Wide supply voltage range from 2.0 to 6.0 V
  • CMOS low power dissipation
  • High noise immunity
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
  • Input levels:
    • For 74HC00: CMOS level
    • For 74HCT00: TTL level
  • Complies with JEDEC standards:
    • JESD8C (2.7 V to 3.6 V)
    • JESD7A (2.0 V to 6.0 V)
  • ESD protection:
    • HBM JESD22-A114F exceeds 2000 V
    • MM JESD22-A115-A exceeds 200 V
  • Multiple package options
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
  • uitable for surface-mounted design
  • Low differential resistance
  • AEC-Q101 qualified

DOWNLOADS:

Quick view

74HC02D

Quad 2-input NOR gate

The 74HC02; 74HCT02 is a quad 2-input NOR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

Features and benefits

  • Wide supply voltage range from 2.0 V to 6.0 V
  • CMOS low power dissipation
  • High noise immunity
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
  • Input levels:
    • For 74HC02: CMOS level
    • For 74HCT02: TTL level
  • Complies with JEDEC standards:
    • JESD8C (2.7 V to 3.6 V)
    • JESD7A (2.0 V to 6.0 V)
  • ESD protection:
    • HBM JESD22-A114F exceeds 2000 V
    • MM JESD22-A115-A exceeds 200 V
  • Multiple package options
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C

DOWNLOADS:

Quick view

74HC04D

Hex inverter

The 74HC04; 74HCT04 is a hex inverter. The inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.

Features and benefits

  • Wide supply voltage range from 2.0 V to 6.0 V
  • CMOS low power dissipation
  • High noise immunity
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
  • Complies with JEDEC standards:
    • JESD8C (2.7 V to 3.6 V)
    • JESD7A (2.0 V to 6.0 V)
  • Input levels:
    • For 74HC04: CMOS level
    • For 74HCT04: TTL level
  • ESD protection:
    • HBM JESD22-A114F exceeds 2000 V
    • MM JESD22-A115-A exceeds 200 V
  • Multiple package options
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C

DOWNLOADS:

Quick view

74HC08D

Quad 2-input AND gate

The 74HC08; 74HCT08 is a quad 2-input AND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

Features and benefits

  • Wide supply voltage range from 2.0 V to 6.0 V
  • CMOS low power dissipation
  • High noise immunity
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
  • Input levels:
    • For 74HC08: CMOS level
    • For 74HCT08: TTL level
  • Complies with JEDEC standards:
    • JESD8C (2.7 V to 3.6 V)
    • JESD7A (2.0 V to 6.0 V)
  • ESD protection:
    • HBM JESD22-A114F exceeds 2000 V
    • MM JESD22-A115-A exceeds 200 V
  • Multiple package options
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C

DOWNLOADS:

Quick view

74HC125D

Quad buffer/line driver; 3-state

The 74HC125; 74HCT125 is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A HIGH on nOE causes the outputs to assume a high impedance OFF-state. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

Features and benefits

  • Wide supply voltage range from 2.0 to 6.0 V
  • CMOS low power dissipation
  • High noise immunity
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
  • Complies with JEDEC standards:
    • JESD8C (2.7 V to 3.6 V)
    • JESD7A (2.0 V to 6.0 V)
  • Input levels:
    • The 74HC125: CMOS levels
    • The 74HCT125: TTL levels
  • ESD protection:
    • HBM JESD22-A114F exceeds 2000 V
    • MM JESD22-A115-A exceeds 200 V
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C

DOWNLOADS:

Quick view

74HC132D

Quad 2-input NAND Schmitt trigger

The 74HC132; 74HCT132 is a quad 2-input NAND gate with Schmitt-trigger inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. Schmitt trigger inputs transform slowly changing input signals into sharply defined jitter-free output signals.

Features and benefits

  • Wide supply voltage range from 2.0 to 6.0 V
  • CMOS low power dissipation
  • High noise immunity
  • Unlimited input rise and fall times
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
  • Complies with JEDEC standards:
    • JESD8C (2.7 V to 3.6 V)
    • JESD7A (2.0 V to 6.0 V)
  • ESD protection:
    • HBM JESD22-A114F exceeds 2000 V
    • MM JESD22-A115-A exceeds 200 V
  • Multiple package options
  • Specified from −40 °C to +85 °C and from −40 °C to +125 °C

DOWNLOADS:

Quick view

74HC138D

3-to-8 line decoder/demultiplexer; inverting

The 74HC138; 74HCT138 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion to a 1-of-32 (5 to 32 lines) decoder with just four '138 ICs and one inverter. The '138 can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

Features and benefits

  • Wide supply voltage range from 2.0 to 6.0 V
  • CMOS low power dissipation
  • High noise immunity
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
  • Demultiplexing capability
  • Multiple input enable for easy expansion
  • Ideal for memory chip select decoding
  • Active LOW mutually exclusive outputs
  • Input levels:
    • For 74HC138: CMOS level
    • For 74HCT138: TTL level
  • Complies with JEDEC standards:
    • JESD8C (2.7 V to 3.6 V)
    • JESD7A (2.0 V to 6.0 V)
  • ESD protection:
    • HBM JESD22-A114F exceeds 2000 V
    • MM JESD22-A115-A exceeds 200 V
  • Multiple package options
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C

DOWNLOADS:

Quick view

74HC14D

Hex inverting Schmitt trigger

The 74HC14; 74HCT14 is a hex inverter with Schmitt-trigger inputs. This device features reduced input threshold levels to allow interfacing to TTL logic levels. Inputs also include clamp diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. Schmitt trigger inputs transform slowly changing input signals into sharply defined jitter-free output signals.

Features and benefits

  • Wide supply voltage range from 2.0 to 6.0 V
  • CMOS low power dissipation
  • High noise immunity
  • Unlimited input rise and fall times
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
  • Complies with JEDEC standards:
    • JESD8C (2.7 V to 3.6 V)
    • JESD7A (2.0 V to 6.0 V)
  • ESD protection:
    • HBM JESD22-A114F exceeds 2000 V
    • MM JESD22-A115-A exceeds 200 V
  • Multiple package options
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C

DOWNLOADS:

Quick view