UC3844ST SOIC8
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7812ST TO263
The L78 series of three-terminal positive regulators is available in TO-220, TO-220FP, D²PAK and DPAK packages and several fixed output voltages, making it useful in a wide range of applications.
These regulators can provide local on-card regulation, eliminating the distribution problems associated with single point regulation. Each type embeds internal current limiting, thermal shut-down and safe area protection, making it essentially indestructible. If adequate heat sinking is provided, they can deliver over 1 A output current. Although designed primarily as fixed voltage regulators, these devices can be used with external components to obtain adjustable voltage and currents.
78L12ST SOIC
The L78L series of three-terminal positive regulators employ internal current limiting and thermal shutdown, making them essentially indestructible. If adequate heat-sink is provided, they can deliver up to 100 mA output current. They are intended as fixed voltage regulators in a wide range of applications including local or on-card regulation for elimination of noise and distribution problems associated with single-point regulation. In addition, they can be used with power pass elements to make high-current voltage regulators. The L78L series used as Zener diode/resistor combination replacement, offers e improvement along with lower quiescent current and lower noise.
CD4021ST SOIC
The HCF4021 is a monolithic integrated circuit fabricated in metal oxide semiconductor technology available in PDIP-16 and SO-16 packages.
This device is an 8-stage parallel or serial-input/serial-output register having common clock and parallel/serial control inputs, a single serial data input, and individual parallel "jam" inputs to each register stage. Each register stage is a D-type, master-slave flip-flop in addition to an output from stage 8. "Q" outputs are also available from stages 6 and 7. Serial entry is synchronous with the clock but parallel entry is asynchronous.
In this device, entry is controlled by the parallel/serial control input. When the parallel/serial control input is low, data are serially shifted into the 8-stage register synchronously with the positive transition of the clock line. When the parallel/serial control input is high, data are jammed into the 8-stage register via the parallel input lines and synchronous with the positive transition of the clock line. The clock input of the internal stage is “forced” when asynchronous parallel entry is made. Register expansion using multiple packages is permitted.
